1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing a semiconductor device and, more particularly, to a fabrication method which furnishes anti-punchthrough protection.
2. Description of the Related Art
As CMOS integrated circuit technology has evolved, the size of CMOS transistor geometry is continually reduced. As CMOS gate lengths are reduced, the risk of a short-channel effect, called punch-through, rises. Punch-through is a circuit breakdown in which the drain voltage reaches a sufficiently large value that the depletion layer associated with the drain spreads across the substrate and reaches the source. This causes a destructive source/drain conduction path or leakage current.
Various approaches have been taken to avoid short-channel effects. One technique for avoiding punch-through is to raise the well or substrate dopant concentration, reducing the size of the depletion region so that punch-through does not occur when a voltage is applied. However, increasing the well concentration has drawbacks. The high substrate doping level causes a high source/drain junction capacitance, a low junction breakdown voltage, an increase in transistor threshold voltage and high body effects. Furthermore, a high well concentration reduces carrier mobility, leading to a lowering of drive current.
As an alternative to raising the dopant concentration generally throughout the well or substrate, anti-punchthrough (APT) implants have been developed. APT implants increase dopant concentrations only in the vicinity of the channel and source/drain region, not throughout the entire substrate. However, APT implants suffer similar drawbacks of high body effect, low carrier mobility and high junction capacitance. A specialized APT implant, called a HALO implant, is a self-aligned APT implant in which the polysilicon gate acts as a mask during implant. This mask prevents the channel region from reaching a concentration of dopant that is too heavy. HALO implants appear to lower body effect and prevent mobility degradation, nonetheless, source and drain junction capacitance remains elevated. Improvements to HALO implants have led to development of a large-angle HALO implant in which dopant ions are bombarded at a large angle, allowing the APT implant to reach regions overlaid by the polysilicon gate. For large-angle HALO implants, junction capacitance remains high if the large-angle implant is deeper than the source/drain junction but, if the large-angle implant is sufficiently shallow with respect to the source and drain, the junction capacitance does not increase. However, a shallow large-angle HALO implant may fail to block the punch-through path beneath the source and drain.
One promising APT approach is called a self-aligned pocket implant in which the APT implant is formed as a small pocket of a heavy dopant concentration. The APT pocket blocks the potential leakage path while allowing the channel region to maintain a lower dopant concentration. Thus, rather than raising the well concentration uniformly throughout the substrate, the self-aligned pocket implant raises dopant concentrations only where the increased doping is needed. One self-aligned pocket implant technique is described by Hori A. ("High Carrier Velocity and Reliability of Quarter-Micron SPI (Self-aligned Pocket Implantation) MOSFETS", IEDM 92-699, December 1992). Following the method of the Hori process, a localized pocket implant is formed using the gate electrode and a titanium silicide (TiSi.sub.2) as self-aligned masks. There are some disadvantages to the Hori process. The masking properties of TiSi.sub.2 are not well known so that the masking capability and the TiSi.sub.2 layer thickness needed to appropriately mask a particular dopant are not established. Furthermore, the TiSi.sub.2 layer thickness that is necessary for masking purposes may be incompatible with other requirements of the integrated circuit. In addition, the spacer must be removed while leaving the salicide (TiSi.sub.2) and other dielectrics in the circuit undisturbed. Removing the spacer in this manner is a difficult procedure in a manufacturing environment.